Various embodiments of this disclosure relate to high-performance symmetric multiprocessing (SMP) and, more particularly, to dynamic synchronous to asynchronous frequency transitions in high-performance symmetric multiprocessing.
When an n-way SMP network is used in a computer system, the processor cores of the computer system are typically distributed across many processors, which are connected together using high-performance buses that run synchronously with the processor cores. Together, these high-performance buses and any other components connecting the processors together make up an interconnect between the processors. Synchronicity across the processor cores minimizes delay in moving data across the interconnect between processors in the SMP network. To save power at the system level, it is desirable to have the ability to slow the frequency of some processor cores during periods of low system activity, but doing so can result in asynchronous operation.
Traditionally, slowing down a processor core requires the SMP network as a whole to slow down as well, to maintain the synchronicity between the processor core in question and the interconnect. The interconnect will generally have operating parameters, requiring it to run at a certain frequency or range of frequencies. Thus, the entire SMP network cannot be slowed to save power, and a processor core may be required to run at a different frequency than the interconnect to achieve power savings. Thus, it is sometimes necessary to independently scale the rates of processors and interconnect buses when entering a power-save mode. Some techniques exist for dynamically switching between synchronous and asynchronous operation, but these techniques lack the desired level of performance.